(a) Field of the Invention
The present invention relates to a static random access memory (static RAM) having a high-resistance load in a memory cell and, in particular, to a technique for achieving a stable resistance for the high-resistance load of a memory cell.
(b) Description of the Related Art
A high-resistance load static RAM comprises a pair of driver transistors, a pair of transfer gate transistors, and a pair of high-resistance loads associated with the pair of driver transistors in each memory cell. The high-resistance load is connected via a through-hole to the gate electrode of the driver transistor and a storage node which is implemented as an extension of the source of the transfer gate transistor. The through-hole generally receives therein a olycrystalline silicon (polysilicon) or semi-insulating polysilicon (SIPOS) film, which is doped with impurities only at the through-hole portion thereof to lower the resistivity of the polysilicon or SIPOS film. Or alternatively, the high-resistance load is connected to the storage node and the gate electrode by a thin undoped polysilicon film.
FIG. 1 shows a conventional static RAM having a thin undoped polysilicon film as mentioned above. A field oxide film 12 separates the surface of a silicon substrate 11 into a plurality of cell areas 30, wherein diffused regions 16a, 16b and 16c are disposed for the cell transistors. Gate electrodes 14a and 14b each having a side-wall oxide film 15 are formed on a gate oxide film 13 formed in the cell area 30. A first interlevel dielectric film 17 covers these transistor elements and has a through-hole 31c for exposing the diffused region 16c, to which a ground line 18 is connected. Further, above these elements is formed a second interlevel dielectric film 19, on which a high-resistance load 20 made of a SIPOS film is disposed.
A through-hole 31b is formed in the first and second interlevel dielectric films 17 and 19 for exposing a portion of the gate electrode 14b of the driver transistor and a storage node 16b formed as an extension of the source of the transfer gate transistor. A low-resistance polysilicon contact film 24E is formed in the through-hole 31b to connect the high-resistance load 20 with the gate electrode 14b of the driver transistor and the storage node 16b.
The low-resistance polysilicon contact film 24E has an extension overlying the high-resistance load 20 in a stacked configuration. A third interlevel dielectric film 21 covers these elements, and a digit line 22 is formed thereon to be connected to the drain of the transfer gate transistor by means of through-hole 31a. A passivation film 23 covers the entire area for protection.
In the conventional static RAM having a high resistivity load as described above, the effective resistive load of the memory cell is determined by the overall resistance of the low-resistance polysilicon contact film 24E and the high-resistance load 20, which fact involves a large variation and an undesirable low resistance in the overall resistance. On the other hand, a larger resistivity, if selected for the polysilicon film 24E to obtain a sufficient larger overall resistance, involves a larger connection resistance between the storage node 16b and the gate electrode 14b of the driver transistor. Namely, a stable effective resistive load and a low connection resistance between the storage node and the gate electrode of the driver transistor are tradeoffs in the memory cell.
Patent Publication JP-A-3-157966 describes another configuration of a memory cell, wherein driver transistors and transfer gate transistors are implemented by a first semiconductor film, a high-resistance load is implemented by a second semiconductor film, and a ground line is implemented by a third semiconductor film.